1. Field of the Invention
The present invention relates to a semiconductor memory and more particularly to a redundancy circuit for a first-in first-out (hereinafter referred to as FIFO) memory for selecting memory cells by means of an address part.
2. Description of the Background Art
FIG. 26 is a conventional two-port FIFO memory including a redundancy circuit. In FIG. 26, reference numeral 1 designates a memory cell array including a plurality of memory cells arranged in matrix form; 7 designates a regular memory cell forming the memory cell array 1; reference character 7a designates a spare memory cell for redundancy forming the memory cell array 1; 170 designates a word address counter for outputting the count of pulses of a write clock signal WT; 171 designates a write word address decoder for decoding the count of the write word address counter 170; 172 designates a read word address counter for outputting the count of pulses of a read clock signal RT; 173 designates a read word address decoder for decoding the count of the read word address counter 172; 174 designates a write bit address counter for outputting the count of pulses of the write clock signal WT; 175 designates a write bit address decoder for decoding the count of the write bit address counter 174; 176 designates a read bit address counter for outputting the count of pulses of the read clock signal RT; 177 designates a read bit address decoder for decoding the count of the read bit address counter 176; 178 designates a spare memory cell array; 179 designates a redundancy decoder for decoding the count of the write bit address counter 174 or the read bit address counter 176; and 180 designates a fuse.
Operation will be described below. In the write operation of data into the memory cells 7 included in the memory cell array 1, the selection of a specific memory cell 7 in the memory cell array 1 is achieved such that the write word address decoder 171 and write bit address decoder 175 decode the counts of the write word address counter 170 and write bit address counter 174 which increase in synchronism with the write clock signal WT. In the read operation of data from the memory cells 7 included in the memory cell array 1, the selection of a specific memory cell 7 in the memory cell array 1 is achieved such that the read word address decoder 173 and read bit address decoder 177 decode the counts of the read word address counter 172 and read bit address counter 176 which increase in synchronism with the read clock signal RT.
When a fault is developed in a regular memory cell 7, the fuse 180 of the bit line connected to the defective memory cell 7 is cut off by means of laser blowing or the like. The insufficient memory capacitance is compensated for by the spare memory cell array 178. The redundancy decoder 179 is processed by means of laser blowing such that it decodes only the count to be decoded for the bit line whose fuse 180 is cut off. The number of sets of spare memory cell arrays 178 and redundancy decoders 179 to be prepared is arbitrary. When the redundancy memory is unnecessary, the fuse 180 of the bit line connected to the spare memory cells 7a is cut off by means of laser blowing or the like.
The conventional semiconductor memory has drawbacks to be described below. Since a fault might be developed in a memory cell 7 in the memory cell array 1, it is necessary to provide the fuse 180 for redundancy for each bit line, resulting in a need for a large area for the fuses 180.
The address decoders of the FIFO memory require no counter and is easily formed by a shift register including flip-flop circuits connected in series. However, it is difficult to provide a redundancy circuit in the FIFO memory.
It is further difficult to provide redundancy in relation to a start address in the FIFO memory.